To improve an operation margin in an internal circuit included in a large-scale integration (LSI) chip or another semiconductor device, a timing of an internal signal is adjusted by a variable delay control circuit to change an operation timing of the internal circuit. A test circuit including a control gate and the like is added to this type of variable delay control circuit, and a test signal is given to an input terminal of the variable delay control circuit. By deciding a logical value that appears at an output terminal of the variable delay control circuit when the test signal is given, it is possible to diagnose whether a stuck-at fault is present in the variable delay control circuit. A stuck-at fault is a fault that occurs when a signal line causes a short, a break, or another failure and is stuck at a logical 0 or logical 1.
A clock generating circuit is proposed in which an input clock is given to the first one of four variable delay control circuits coupled in series and four delay clocks output from the four variable delay control circuits are used to create a transition edge of an output clock. In the clock generating circuit, the delay times of the variable delay control circuits are adjusted so that the phase of a delay clock output from the last variable delay control circuit matches the phase of the input clock, so an output clock that has a frequency twice the frequency of the input clock and has a 50% duty cycle is generated. To detect a difference, caused due to manufacturing error or the like, in delay time between variable delay control circuits, a common test signal is supplied to a plurality of variable delay control circuits, which are electrically separated, and the output level of an exclusive logical sum circuit that receives outputs from any two variable delay control circuits is held in a latch.
Japanese Laid-open Patent Publication Nos. 11-101852, 5-291901, and 8-8699 are known as examples of related art.
As the clock frequency of a semiconductor device is increased, the timing margin of an internal signal transmitted in the semiconductor device tends to be reduced. As the structures of transistors and other elements included in a semiconductor device are made to be fine, stuck-at faults caused in a semiconductor device manufacturing process tend to be increased. A stuck-at fault is detected by supplying a test pattern to the semiconductor device and comparing a value output from the semiconductor device with an expected value. However, the more complex the test pattern is, the longer a test time is, increasing the manufacturing cost of the semiconductor device.